As technology advances, memories in semiconductor devices have become more and more dense. While such compact memory provides greater functionality, cells within the semiconductor memories become more and more susceptible to the presence of defects which could impede or corrupt the flow of data within the semiconductor. Defects in semiconductor memories occur during the fabrication, packaging, and field operation of an integrated circuit. Additionally, such defects may include wafer defects, oxide defects, metalization defects, interconnect defects, contamination defects, unintended or missing connections, missing or extra contacts, and others.
To overcome the presence of defects in circuits of a semiconductor device, circuit redundancy is utilized to bypass data paths affected by a defect while preserving the original addresses of the affected data paths. For example, a memory array may include a plurality of normally-used columns of memory cells plus one or more redundant columns of memory cells. When a normally-used column is found to be defective, it is desired to discontinue use of the defective column and initiate use of a redundant column. Many devices have been provided for substituting a redundant row or block of memory cells for a faulty row or block of cells. For example, U.S. Pat. No. 5,301,153 discloses a memory array (32) which includes a column of redundant memory cells (40). A series of multiplexers are then used to determine when the data provided by the column of redundant memory cells should be used rather than data provided by the column of the normally-used memory array (34). Additionally, U.S. Pat. No. 5,204,836 discloses an apparatus for switching arrays of memory cells to correct for defects in the memory data structure. Toggle switches are used to "steer" data to one of the redundant memory cell arrays when a defect is detected.
FIG. 1 illustrates a portion of a prior art data processing system 100. During operation of this prior art system, when a defect is detected in a portion of a plurality of memory cells 112, a redundancy control circuit 110 indicates that a portion of redundant wordlines 130, also called redundant rows, should be accessed rather than the originally addressed memory cells. Furthermore, redundancy control circuit 110 selects a multiplexer structure (not shown in detail herein) to output data provided by a portion of the redundant bit lines 114, also called redundant columns, upon detection of a defect. To enable the portion of redundant bitlines 114 to be accessed rather than the addressed portion of the memory cells 112, redundancy control circuit 110 provides a Bit Address signal to bitline decoder 118. An output of redundant bitlines 114 is selected by bitline decoder 118 and provided to input/output circuit 120 in place of the originally addressed memory cells.
In addition to providing redundant bitlines, prior art data processing systems also provided redundant wordlines, such as redundant wordlines 130. To enable the portion of redundant wordlines 130 to be accessed rather than the addressed portion of the memory cells 112, redundancy control circuit 110 provides a redundant address to redundant wordline decoders 132. Redundant wordline decoders 132 subsequently decode the redundant address to access redundant wordlines 130. As with the portion of redundant bitlines 114, an output of redundant wordlines 130 is provided to bitline decoder 118 and subsequently to input/output circuit 120.
It should be noted that during operation of this prior art system, wordline decoder 108 provides control signals to the wordlines running throughout the plurality of memory cells 112 and throughout redundant bit lines 114. Additionally, a same portion of bitline decoder 118 would be provided to enable a preselected portion of memory cells 112 to output data. Furthermore, in prior art data processing system 100, input/output circuit 120 is required to multiplex a data value provided by redundant bit lines 114 with each of the outputs provided by the plurality of memory cells 112 as normally accessed. While the use of redundant bitlines 114 and redundant wordlines 130 does provide some flexibility in correcting defects within memory cells 112, the use of redundant bit lines 114 and redundant wordlines 130 still requires the use of wordline decoder 108, bitline decoder 118, and input/output circuit 120. If a defect occurs in either of wordline decoder 108, bitline decoder 118, or input/output circuit 120, methods for correcting these defects are limited to defects which typically cause isolated failures along one or two wordlines or bitlines.
To correct such defects, prior art systems may implement a redundant element which includes "n" bitlines, a column decoder and a sense amp as a replacement for bitline failures. Thus, there are some methods for correcting the defects of a column decoder or a sense amp. However, due to area constraints within a semiconductor data processor, usually only a minimal number of such redundant elements are included. Furthermore, even with the use of such redundant elements, it is difficult to correct a defect in the row or column decoder unless it is unique to one row or wordline driver. For example, if there is a short between two bitlines that did not share the same sense amp, then two redundant elements would be required. As printed geometries become smaller and smaller, the capacities of reducing defect sizes does not necessarily keep pace. Therefore, large defects may cause failures in multiple cells, decoders, and sense amps. Additionally, gross scratches are generally so large that hundreds of memory cells may be impacted. Such defects may not be compensated for by the prior art systems described above.
As well, in some prior art systems, a local wordline may be used to access only a block of cells of a memory array. Thus, if the portion of the data processing system 100 illustrated in FIG. 1 included a local wordline implementation, only a portion of memory cells would be accessed when that wordline was asserted. For more information on local wordline redundancy implementations, refer to "Building Fast SRAMs With No Process `Tricks`," published in Electronics in Aug. 7, 1986, pp. 81-83.
While the methodologies of the prior art implementations described herein are representative of typical redundancy techniques, these techniques have certain deficiencies. In each of these cases, the redundant cell structures are provided to correct for defects in memory cells. However, neither of these structures provides a methodology, system, or circuit for correcting defects in the circuitry controlling access to and from each of the cells in the memory array when those defects impact more than one column decoder or sense amp, or which short wires that affect the decoding of multiple rows or columns. For example, if there is a defect in a row decoder, a column decoder, or a sense amp in either of the prior art redundant circuits, the memory cells associated with those circuits may not be accessed and the semiconductor device on which they are implemented will fail.